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In electronic design automation, a floorplan of an integrated circuit is a schematic representation of tentative placement of its major functional blocks. In modern electronic design process floorplans are created during the floorplanning design stage, an early stage in the hierarchical approach to integrated circuit design. Depending on the design methodology being followed, the actual definition of a floorplan may differ. ==Floorplanning== Floorplanning takes in some of the geometrical constraints in a design. Examples of this are: * bonding pads for off-chip connections (often using wire bonding) are normally located at the circumference of the chip; * line drivers often have to be located as close to bonding pads as possible; * chip area is therefore in some cases given a minimum area in order to fit in the required number of pads; * areas are clustered in order to limit data paths thus frequently featuring defined structures such as cache RAM, multiplier, barrel shifter, line driver and arithmetic logic unit; * purchased intellectual property blocks (IP-blocks), such as a processor core, come in predefined area blocks; * some IP-blocks come with legal limitations such as permitting no routing of signals directly above the block. 抄文引用元・出典: フリー百科事典『 ウィキペディア（Wikipedia）』 ■ウィキペディアで「Floorplan (microelectronics)」の詳細全文を読む スポンサード リンク
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